1. Field of the Invention
The present invention generally relates to an image processing apparatus, and more particularly to an image processing apparatus which processes image data so as to display a certain image on a screen of a CRT display unit under a control of a central processing unit (CPU), for example.
2. Prior Art
Recently, several kinds of image processing apparatuses are developed and quite effective for displaying an image corresponding to image data stored in a video random memory (VRAM) on the screen of the CRT display unit under the control of the CPU.
FIG. 1 is a block diagram showing a general image display system employing a conventional image processing apparatus. In FIG. 1, an image processing apparatus 1 performs an image display on a screen of a CRT display unit 3 under a control of a CPU 2. In addition, a VRAM 4 stores dot data for the image display and character codes, and a character generator 5 used for a character display stores character patterns. The character pattern designated by the character code stored in the VRAM 4 is read from the character generator 5. Furthermore, a memory 7 employs a read only memory (ROM) for storing programs used in the CPU 2.
In some cases, the image processing apparatus 1 is required to perform a block transfer such that a certain part of the image data stored in a certain area of the VRAM 4 is transferred to another area of the VRAM 4. For example, the above cases include a case where a image displayed at a certain position on a display screen of the CRT display unit 3 must be moved to another position, a case where the image data stored in a non-display area of the VRAM 4 must be transferred to a display area of the VRAM 4 so as to display the image thereof on the display screen of the CRT display unit 3, and a case where the image data stored in the display area must be transferred to the non-display area.
In some cases, one of or both of boundaries of a source area and a destination area do not align with a word boundary in the above-mentioned block transfer FIG. 2 shows a memory map of the VRAM 4 representing a case where the boundaries of both of the source and destination areas do not align with the word boundaries, for example. In FIG. 2, each of block sections divided by full lines represents a one word area, a hatched portion S designates the source area, and another hatched portion D designates the destination area. As shown in FIG. 2, the boundaries (shown by dashed lines) of both of the source area S and the destination area D do not align with the word boundaries, and such boundaries are located at middle positions of words.
As described heretofore, the conventional image display system suffers a problem in that a process for a data transfer becomes quite complicated when one of or both of the boundaries of the source and destination areas do not align with the word boundaries. The reason why such process becomes complicated is that each of memories constituting the VRAM 4 can not perform a data access by a one word unit and it is therefore necessary to transfer a bit boundary in the word where each of the boundaries of the source and destination areas is located. More specifically, the conventional system must need a mask process for read data and write data and other processes, hence, the conventional system suffers a problem in that processes of the CPU 2 must be quite complicated. Such problem must be caused in both of a character mode and a graphic mode similarly.
Therefore, the conventional image processing apparatus is disadvantageous in that loads for programs must be increased so that a transfer speed thereof must be delayed when a transfer of bit boundaries is performed.
In order to obtain several effects of an image process, the image processing apparatus performs a logical operation between source data and destination data or among the source and destination data and other pre-stored data, and data representative of the operation result are written in the destination area. However, there are no conventional apparatus which can perform both of the transfer of bit boundaries and the logical operation at one time, and such apparatus is demanded to be developed in these days.
FIG. 3 is a block diagram showing another image display system employing another conventional image processing apparatus (or a conventional display control apparatus) 11. In FIG. 3, 12 designates a CPU, 13 designates a memory consisting of a ROM for storing programs used for the CPU 12 and a RAM for storing data, 14 designates a bus line, 15 designates a VRAM, and 16 designates a CRT display unit. In this case, the image processing apparatus 11 writes display data (or the image data) outputted from the CPU 12 in the VRAM 15. The image processing apparatus 11 sequentially reads such display data from the VRAM 15 by a timing of a predetermined dot clock so as to convert the read display data into three color signals representative of three primary colors R (red), G (green) and B (blue). Such color signals with a synchronizing signal are outputted to the CRT display unit 16 wherein an image corresponding to the display data stored in the VRAM 15 is displayed on a display screen thereof.
In the case where the CPU 12 reads the display data from the VRAM 15 in the above-mentioned image display system, the CPU 12 outputs addresses and a memory read signal for the VRAM 15 to the image processing apparatus 11 via the bus line 14. Hence, the image processing apparatus 11 outputs a wait signal to the CPU 12 at first. Due to the wait signal, processes of the CPU 12 are subjected to a standby state. Next, the image processing apparatus 11 waits for a timing which enables a memory access and such apparatus 11 thereafter starts to read the display data from the VRAM 15. Thereafter, the image processing apparatus 11 turns off the wait signal so that the data read from the VRAM 15 are outputted to the bus line 14. The CPU 12 reads such data at an end timing of a memory read cycle.
As described above, in the case where the CPU 12 reads the data from the VRAM 15, the conventional image processing apparatus 11 must output the wait signal to the CPU 12 at each time when the CPU 12 outputs the addresses and the memory read signal thereto, and the apparatus must turn off the wait signal when the display data are read from the VRAM 15.
Meanwhile, there exists a case where the CPU 12 does not need the data read from the VRAM 15. For example, in the case where data stored in a first area of the VRAM 15 are transferred to a second area of the VRAM 15, the CPU 12 does not read the data which are read from the VRAM 15 based on the addresses and the memory read signal outputted from the CPU 12. Instead, such data are once stored in the image processing apparatus 11 and then written in the second area of the VRAM 15 in many cases. (However, such process differs depending on a construction of the image processing apparatus 11.)
However, the conventional image processing apparatus 11 must output the wait signal to thereby stop the process of the CPU 12 even in the above-mentioned case. Therefore, the conventional system suffers a problem in that a usage efficiency of the CPU 12 must be lowered.